• Ts Desired sampling period. Generated usually from an external clock.
• TL Latency time. The time taken to stop the foreground task and start the real-time section.
• Tj Jitter: is the difference between minimum latency time and instantaneous latency time.
• Te Effective sampling period. The time between the previous sample and the next sample.
• Tc Computation delay. The time taken to execute the code in the interrupt service routine.
• Tf Foreground time. The time remaining for foreground tasks before the next interrupt occurs.

Usually the hardware timer generates an interrupt of a fixed (and unwavering) period Ts. When the interrupt occurs, the processor stops executing what it is doing (foreground task) and starts executing the real-time controller or the Interrupt Service Routine (ISR). The time taken between the occurrence of the hardware interrupt and the actual start of the ISR is the latency period TL. Ideally this duration should be as small as possible. More importantly, this duration should be as constant as possible. The time between the start of one ISR execution and the start of the next ISR execution is the effective sampling period Te. This value should be as close as possible to Ts. If TL is constant, then Te = Ts and the ISR is only delayed by TL. However, due to Jitter the effective sampling period is not constant. Jitter causes noise and unwanted harmonics in the control signal especially when differentiation is required. Maximum latency imposes a constraint on maximum sample rate. The time it takes to execute the ISR is termed the computation delay Tc and should be less than the effective sampling period Te or the system will skip control cycles. The time taken between the end of two ISR executions is the time remaining in the foreground, Tf, for the processor to perform other tasks such as maintaining the GUI and running other programs.